◎半導体後工程に関連した最新技術を扱う国際会議ECTC2022での発表を分かりやすくレビュー。
◎解説するテーマは、各種インターポーザ、チップレット、3D-IC/TSV、Cu-Cuハイブリッド接合等に関連したプロセス技術・材料技術です。先端パッケージング・実装技術の最新動向の把握、情報収集にお役立てください。
1. ECTCの紹介と最近の研究動向、および用語の説明
1.1 ECTCの発表件数の推移や国別／研究機関別投稿状況
1.2 3D-IC/TSV技術（Via-middle vs. Via-last, Wafer-on-Wafer vs. Chip-on-Wafer他）
1.3 FOWLP（Fan-Out Wafer-Level Packaging）とCoWoS (Chip-on-Wafer-on-Substrate)
1.4 チップレット
2. RDLインターポーザ 9件
2.1 Session 1: Advanced Packaging for Heterogeneous Integration and High Performance Computing
・Paper 1. Organic Interposer CoWoS-R+(plus) Technology 【TSMC】
・Paper 6. 2.3D Hybrid Substrate with Ajinomoto Build-Up Film for Heterogeneous Integration 【Unimicron】
2.2 Session 19: Advances in Fan-Out Panel Level Packaging
・Paper 5. Panel-Based Large-Scale RDL Interposer Fabricated Using 2-Micron Pitch Semi-Additive Process
for Chiplet-Based Integration【DNP】
2.3 Session 20: Enhancements in Fine-Pitch Interconnects, Redistribution Layers and Through-Vias
・Paper 1. A Study of Failure Mechanism in the Formation of Fine RDL Patterns and Vias
for Heterogeneous Packages in Chip Last Fan-Out Panel Level Packaging 【Samsung】
2.4 Session 30: High-Speed Challenges in Power and Signal Integrity
・Paper 3. Optimization of 2.5D Organic Interposer Channel for Die and Chiplets【Applied Materials】
2.5 Session 31: Fan-Out Packaging Technologies and Applications
・Paper 4. Advanced Chip Last Process Integration for Fan-Out Wafer Level Packaging (WLP) 【Samsung】
・Paper 6. Chip-Last FOWLP Based Antenna-in-Package (FO-AiP) for 5G mmWave Application 【RFcore】
2.6 Session 37: Interactive Presentation 1
・Paper 11. Mechanical and Thermal Characterization Analysis of Chip-Last Fan-Out Chip on Substrate【ASE】
2.7 Session 39: Interactive Presentation 3
・Paper 2. Chip Last Fan-Out Chip on Substrate (FOCoS) Solution for Chiplets Integration 【ASE】
3. Si Bridge ４件
3.1 Session 13: Technologies for Heterogeneous Integration, Automotive and Power Electronics
・Paper 7. Dimensional Parameters Controlling Capillary Underfill Flow for Void-Free Encapsulation
of a Direct Bonded Heterogeneous Integration (DBHi) Si-Bridge Package 【IBM Japan】
3.2 Session 14: Novel Bonding and and Stacking Technologies
・Paper 7. Characterization of Non-Conductive Paste Materials (NCP) for Thermocompression
Bonding in a Direct Bonded Heterogeneously Integrated (DBHi) Si-Bridge Package 【IBM Japan】
3.3 Session 15: Enhanced Methods & Processes for Heterogeneous Integration Assembly
・Paper 1. Super Fine Jet Underfill Dispense Technique for Robust Micro Joint in Direct Bonded
Heterogeneous Integration (DBHi) Silicon Bridge Packages 【IBM Japan】
・Paper 7. A Self-Aligned Structure Based on V-Groove for Accurate Silicon Bridge Placement
【University of Sherbrooke & IBM Canada】
4. 狭ピッチマイクロバンプ 2件
4.1 Session 25: Advancements in 2.5D and 3D Packaging Technology
・Paper 5. Low Temperature Backside Damascene Processing on Temporary Carrier Wafer Targeting
7μm and 5μm Pitch Microbumps for N Equal and Greater Than 2 Die to Wafer TCB Stacking 【IMEC】
4.2 Session 26: Soldered and Sintered Interconnections
・Paper 3. Tight-Pitched 10 m-Width Solder Joints for c-2-c and c-2-w 3D-Integration in NCF Environment
【Tohoku University & SDM】
5. TSV/TGV ４件
5.1 Session 4: Hybrid Bonding and Innovations for 3D Integration
・Paper 4. The Integration of Grounding Plane into TSV Integrated Ion Trap for Efficient Thermal
Management in Large Scale Quantum Computing Device 【Nanyang Technological University】
・Paper 5. Wafer Stacked Wide I/O DRAM with One-Step TSV Technology 【IME】
5.2 Session 27: Interconnection Reliability
・Paper 6. A Comparative Study of the Thermomechanical Reliability of Fully Filled and Conformal Through
Glass Via (TGV) 【Corning】
5.3 Session 34: Processing Enhancements in Fan-Out and Heterogeneous Integration
・Paper 7. Buried Power Rails and Nano-Scale TSV: Technology Boosters for Backside Power Delivery
Network and 3D Heterogeneous Integration 【IMEC】
6. ハイブリッド接合、直接接合 38件
6.1 Session 4: Hybrid Bonding and Innovations for 3D Integration
・Paper 1. 3-Layer Stacking Technology with Pixel-Wise Interconnections for Image Sensors Using
Hybrid Bonding of Silicon-on-Insulator Wafers Mediated by Thin Si Layers 【NHK】
・Paper 2. Wafer to Wafer Hybrid Bonding for DRAM Applications 【SK Hynix】
・Paper 3. Analysis of Die Edge Bond Pads in Hybrid Bonded Multi-die Stacks 【Xperi→Adeia】
・Paper 6. Recess Effect Study and Process Optimization of Sub-10 μm Pitch Die-to-wafer Hybrid Bonding
【UCLA】
・Paper 7. A Performance Testing Method of Bernoulli Picker for Ultra-Thin Die Handling Application
【Samsung】
6.2 Session 5: Bonding Technology: Novel Assembly Methods and Processes
・Paper 1. The Influence of Cu Microstructure on Thermal Budget in Hybrid Bonding 【Xperi→Adeia】
・Paper 2. Collective Die-to-Wafer Self-Assembly for High Alignment Accuracy and High Throughput 3D
Integration 【CEA-LETI】
・Paper 3. Fine-Pitch 30 μm Cu-Cu Bonding by Using Low Temperature Microfluidic Electroless
Interconnection 【ASE & National Taiwan University】
・Paper 5. Investigation of Low Temperature Co-Co Direct Bonding and Co-Passivated Cu-Cu Direct Bonding
【National Yang Ming Chiao Tung University】
・Paper 6. Process and Design Optimization for Hybrid Cu Bonding Void 【Samsung】
6.3 Session 8: Hybrid and Direct Bonding Development and Characterization
・Paper 1. Development of Face-to-Face and Face-to-Back Ultra-Fine Pitch Cu-Cu Hybrid Bonding 【Sony】
・Paper 2. Surface Energy Characterization for Die-Level Cu Hybrid Bonding 【IBM & ASM】
・Paper 3. Comprehensive Study on Advanced Chip on Wafer Hybrid Bonding with Copper/Polyimide
Systems 【Showa Denko Materials & Tohoku University】
・Paper 4. Two-Step Ar/N2 Plasma-Activated Al Surface for Al-Al Direct Bonding
【Nanyang Technological University】
・Paper 5. Novel Ga Assisted Low Temperature Bonding for Fine Pitch Interconnects
【ASE & National Chen Kung University】
・Paper 6. Characterization of Die-to-Wafer Hybrid Bonding Using Heterogeneous Dielectrics 【Samsung】
・Paper 7. Solder and Organic Adhesive Hybrid Bonding Technology with Non-Strip Type Photosensitive
Resin and Injection Molded Solder (IMS) 【IBM Japan & Mitsui Chemicals】
6.4 Session 12: Manufacturing and Assembly Process Modeling
・Paper 5. Numerical Evaluation on SiO2 Based Chip to Wafer Hybrid Bonding Performance by Finite
Element Analysis 【IME】
6.5 Session 14: Novel Bonding and and Stacking Technologies
・Paper 1. Behavior of Bonding Strength on Wafer-to-Wafer Cu-Cu Hybrid Bonding 【Sony】
・Paper 2. Development of Polyimide Base Photosensitive Permanent Bonding Adhesive for Middle to Low
Temperature Hybrid Bonding Process 【HD Microsystems & Showa Denko Materials】
・Paper 3. Direct Bonding Using Low Temperature SiCN Dielectrics 【IMEC】
・Paper 5. Prolongation of Surface Activation Effect Using Self-Assembled Monolayer for Low Temperature
Bonding of Au 【Meisei University】
6.6 Session 16: Hybrid & Direct Bonding Innovation, Optimization & Yield Improvement
・Paper 1. The Wafer Bonding Yield Improvement Through Control of SiCN Film Composition and Cu Pad
Shape 【SK Hynix】
・Paper 2. Low Temperature Wafer-to-Wafer Hybrid Bonding by Nanocrystalline Copper 【ITRI】
・Paper 3. Cu-SiO2 Hybrid Bonding Yield Enhancement Through Cu Grain Enlargement
【Tohoku University , T-Micro & JCU】
・Paper 4. A Holistic Development Platform for Hybrid Bonding 【Applied Materials】
・Paper 5. Low Temperature Fine-Pitch Cu-Cu Bonding Using Au Nanoparticles as Intermediate
【Tsinghua University】
・Paper 6. Wet Atomic Layer Etching of Copper Structures for Highly Scaled Copper Hybrid Bonding and
Fully Aligned Vias 【TEL America】
・Paper 7. A Study on Bonding Pad Structure and Layout for Fine Pitch Hybrid Bonding 【Samsung】
6.7 Session 25: Advancements in 2.5D and 3D Packaging Technology
・Paper 1. A Study on Memory Stack Process by Hybrid Copper Bonding (HCB) Technology 【Samsung】
・Paper 4: 3D Packaging for Heterogeneous Integration 【AMD】
6.8 Session 27: Interconnection Reliability
・Paper 5. Fabrication and Reliability Analysis of Quasi-Single Crystalline Cu Joints by Using
Highly <111>-Oriented Nanotwinned Cu 【National Yang Ming Chiao Tung University】
6.9 Session 32: Advanced Interconnect and Wire Bond Technologies for Flexible Device Applications
・Paper 2. Room-Temperature Cu Direct Bonding Technology Enabling 3D Integration with Micro-LEDs
【Tohoku University】
・Paper 3. Ag to Ag Direct Bonding Via a Pressureless, Low-Temperature, and Atmospheric Stress Migration
Bonding Method for 3D Integration Packaging 【Osaka University】
6.10 Session 37: Interactive Presentation 1
・Paper 9. Numerical Simulation of Cu/Polymer-Dielectric Hybrid Bonding Process Using Finite Element
Analysis 【IME】
6.11 Session 39: Interactive Presentation 3
・Paper 3. Die to Wafer Hybrid Bonding for Chiplet and Heterogeneous Integration: Die Size Effects
Evaluation-Small Die Applications 【Xperi→Adeia】
・Paper 4. Yield Improvement in Chip to Wafer Hybrid Bonding【IME】
6.12 Session 40: Interactive Presentation 4
・Paper 6. A Hybrid Bonding Interconnection with a Novel Low Temperature Bonding Polymer System
【ITRI, Brewer Science, National Tsing Hua University & National Yang Ming Chiao Tung University】
7. その他 ４件
7.1 Session 2: High Performance Dielectric Materials for Advanced Packaging
・Paper 1. Ultra-Thin Mold Cap for Advanced Packaging Technology 【Intel/Towa】
7.2 Session 7: Advanced Flip Chip and Embedded Substrate Technologies
・Paper 4. Functional Interposer Embedded with Multi-Terminal Si Capacitor for 2.5D/3D Applications Using
Planarization and Bumpless Chip-on-Wafer (COW) 【Tokyo Tech, Murata & ITRI】
7.3 Session 5: Bonding Technology: Novel Assembly Methods and Processes
・Paper 7. Laser-Assisted Bonding (LAB) Process and Its Bonding Materials as Technologies Enabling the
Low-Carbon Era 【ETRI】
7.4 Session 14: Novel Bonding and Stacking Technologies
・Paper 6. Mini LED Array Transferred onto a Flexible Substrate Using Simultaneous Transfer and Bonding
(SITRAB) Process and Anisotropic SITRAB Film (ASF) 【ETRI & Nexstar Technology】
□ 質疑応答 □